1. Field of the Invention
The invention relates to a single chip microcomputer having a built-in on screen display device (hereinafter, often abbreviated as "OSD") which, when characters, numerals, or the like are to be displayed on a display such as a CRT, simultaneously conducts control of screen display as a television receiver for displaying a channel, a volume, etc., and control of screen display as a teletext receiver for displaying transmitted teletext data.
2. Description of Related Art
Conventionally, a viewer can set a screen of a television receiver to display characters, and/or patterns indicative of the operation state including a selected channel, and a volume. FIG. 1 is a block diagram showing the configuration of a conventional OSD incorporated in a single chip microcomputer which is used for such display (Japanese Patent Application No. 5-2209 (1993)). In FIG. 1, the reference numeral 16 designates a data bus connected to a central processing unit (hereinafter, abbreviated as "CPU") which is not shown. To the data bus 16, connected are a CRT control register 1 for controlling the ON/OFF state of a CRT, a vertical position register 2 to which the vertical position of the display start point is inputted, a character size register 3 to which data of sizes of fonts to be displayed are inputted, a horizontal position register 4 to which the horizontal position of the display start point is inputted, a display data RAM 5 for storing data of characters or patterns to be displayed, a CRT port control resister 6 for controlling an output circuit 12 which outputs RGB signals, a first mask mode register 13 for setting a mask canceling position when a masking function is used, and a second mask mode register 14 for setting a mask setting position. The reference numeral 7 designates an oscillator for generating a display clock signal for the entire OSD, 8 designates a display position controller for controlling display positions of characters or patterns, 9 designates a display controller for controlling the display operation, 10 designates a character ROM for storing font dot data, 11 designates a shift register for converting a parallel format into a serial format, and 15 designates a mask controller for outputting a mask signal in response to output signals from the first and second mask mode registers
Next, the operation will be described. Referring to FIG. 1, the horizontal synchronizing signal (hereinafter, abbreviated as "HSYNC") and the vertical synchronizing signal (hereinafter, abbreviated as "VSYNC") are supplied to the display position controller 8. The oscillator 7 generates a predetermined frequency while being reset at each HSYNC. The output of the oscillator 7 is used as a basic display clock for the entire OSD, and supplied to the display position controller 8, the display controller 9 and the output circuit 12.
On the other hand, in response to instructions from the CPU, data for displaying desired characters or patterns are inputted through the data bus 16 to the registers and the display data RAM 5. Data in the CRT control register 1 are supplied to the display position controller 8, the display controller 9 and the output circuit 12, to control the ON/OFF state of the character display, etc. Data corresponding to the vertical and horizontal positions at which the character display is to be started are previously inputted to the vertical position register 2 and the horizontal position register 4, and data corresponding to the sizes of fonts to be displayed are previously inputted to the character size register 3. These data are supplied to the display position controller 8. The RGB outputs from the output circuit 12 are controlled depending on the contents of the CRT port control register 6. In the display data RAM 5, addresses are arranged in accordance with the sequence of the character display, and data of characters to be displayed are inputted in the sequence of the addresses. Data stored in the display data RAM 5 include character code data, color code data, display mode data (hereinafter, referred to as "attribute code data"), etc. The attribute code data include data for character modifications such as a blink of displayed characters (blinking), and a display of an underscore.
The display position controller 8 compares the contents of the vertical position register 2 with the count value of the HSYNC, and the contents of the horizontal position register 4 with the count value of the display clock from the oscillator 7. When the two values of each combination coincide with each other, a display enabling signal is issued to the display controller 9, whereby the display controller 9 is activated to start a series of the following operations for displaying characters. First, the display controller 9 supplies the display data RAM 5 with the value which is obtained by counting the character number in the horizontal direction on the basis of the display clock. From the display data RAM 5, character code data, color code data and attribute code data are then outputted in the sequence of display. The color code data and the attribute code data are directly sent to the output circuit 12, and the character code data are supplied to the character ROM 10 so that the corresponding addresses of the character ROM 10 are decoded and font dot data corresponding to the character code data are outputted.
As shown in FIG. 2, for example, one font consists of picture elements of t.times.m dots. When the character ROM 10 stores such fonts for n characters, therefore, the character ROM 10 has a capacity corresponding to t.times.m.times.n dots. The font data read out from the character ROM 10 which are in a parallel format are converted by the shift register 11 into a serial format, and then supplied to the output circuit 12. In addition to the font data, the output circuit 12 receives from the display data RAM 5 the color code data indicative the character color and the background color, and the attribute code data, and conducts the display control on ordinary font data in accordance with the display mode which is indicated by the color code data and the attribute code data. In this way, the output circuit 12 outputs RGB signals, and desired characters or patterns are displayed on a screen in accordance with these signals.
Dot data of a font are stored in the unit of the number of dots arranged in the width direction, in areas of addresses of the character ROM 10 which are produced by decoding the character code data indicative of the font. In the case of FIG. 2, font data of t dots in the longitudinal direction are stored in the unit of one line at t addresses.
When the addresses are indicated in the sequence starting from the upper end by AD.sub.1, AD.sub.2, AD.sub.3, AD.sub.4, .sup.. . . , AD.sub.t-1, and AD.sub.t, dot data are outputted in this sequence from the character ROM 10. The display position controller 8 counts the line number (1 to t) in the longitudinal direction of one character, and sequentially outputs dot data of each line of a display character. These operations are repeated for each of 1 to t lines to complete the character display of one block.
The display position will be described in detail. In FIG. 3 which shows an example of a display screen, the reference numeral 17 designates a display screen for displaying first to fourth display blocks 18 to 21. When a character string to be displayed is defined as one display block, the OSD has a plurality of display blocks in the form of a hardware. Addresses for storing a character code, a color code and an attribute code are assigned to each character in the display blocks. In the following, an example where a screen display using four display blocks is conducted will be described. The vertical position register 2 is preset so that the blocks are displayed in the sequence of the first display block 18.fwdarw.the second display block 19.fwdarw.the third display block 20.fwdarw.the fourth display block 21 (the vertical display start positions are set to be CV1 to CV4, respectively). When the process reaches the vertical display start position CV2 of the second display block 19 in the course of the display of the first display block 18, the last-first control is applied so that the display of the first display block 18 is stopped in the middle and the display of the second display block 19 is started. When the process then reaches the vertical display start position CV3 of the third display block 20 in the course of the display of the second display block 19, the display of the second display block 19 is stopped and the display of the third display block 20 is started. Also in the relationship between the third and fourth display blocks 20 and 21, the display is conducted in the same manner. As described above, in any display block, the priority is assigned to a block having a later vertical display start position. When the vertical display start positions of plural blocks coincide with each other (for example, in the case of CV1=CV2), priorities are assigned to the blocks by means of a hardware, and a display block having a higher priority is displayed. FIG. 4 shows an example of a screen display in the case where priorities are assigned in ascending order of the block numbers. The above-described control is conducted in the display position controller 8.
Next, the masking function will be described. FIG. 5 shows an example of a screen display using the masking function. A displayable area and undisplayable areas are set in a display screen so that RGB signals from the OSE are not outputted in the undisplayable areas. Using the first and second mask mode registers 13 and 14, a mask cancel position, and a mask set position are set respectively. On the basis of these values, the mask controller 15 recognizes the displayable area and the undisplayable areas, and then outputs to the output circuit 12 a signal which enables or disables the output circuit 12 to output RGB signals. When the vertical display start position of the display block is decremented or incremented by using the masking function, it is possible to conduct a scroll display.
Next, the multiline display will be described. FIG. 6 shows an example of a screen display in which the multiline display is conducted. For example, it is assumed that the hardware of the OSD has display blocks only for four lines and the multiline display is conducted when five or more lines are to be displayed. When the display of each display block is terminated, an interrupt occurs (hereinafter, such an interrupt is referred to as "CRT interrupt"). In the case where display areas of two display blocks are over-lapped and the display of the former display block is stopped in the middle, however, an interrupt does not occur. This interrupt causes a program for the multiline display to be executed, and the CPU conducts the following processes in accordance with the program execution. Firstly, the CRT interrupt occurs when the display of the first display block 18 is terminated. The vertical display start position of the first display block 18 is rewritten to be CV5. When the character size is to be changed, the contents of the character size register 3 is rewritten. Furthermore, code data stored in the display data RAM 5 are rewritten. When the vertical display start position reaches CV5 after the rewriting processes are terminated, the first display block 18 is displayed again. Similarly, with respect to the second to fourth display blocks 19 to 21, the above-mentioned data are rewritten by the CPU each time when the CRT interrupt occurs, thereby enabling the multiline display to be conducted.
The case where the conventional OSD processes a plurality of display tasks in which accesses from the CPU are asynchronously conducted will be considered. It is assumed that one display task is a channel selection display process in which a selected channel, a volume, etc. are displayed, and another display task is a teletext display process in which character data transmitted in a teletext are displayed. The first and second display blocks are previously set to conduct the channel selection display, and the third and fourth display blocks to conduct the teletext display. Since data of a teletext are transmitted in the form wherein the data are superimposed on a video signal, data of a teletext are always received. In accordance with the data, therefore, the CPU must sequentially write code data into the display data RAM 5 of the OSD.
When the teletext display is conducted by the multiline display of the third and fourth display blocks 20 and 21, for example, a display for a volume adjustment may be conducted simultaneously. If the display positions are overlapped under this situation, there may arise a case where a desired display cannot be obtained depending on the vertical display start positions and the character sizes. FIG. 7 shows an example of a screen display in such a case. When the teletext display is conducted by the third and fourth display blocks 20 and 21, a channel call "2" is displayed. At this time, the relationship between the vertical display start positions is set to be the last-first control, and therefore the channel call cannot be displayed in an adequate manner. If the vertical display start position of the first display block 18 is made coincident with that of the fourth display block 21, the channel call "2" can be displayed without being hidden. However, this is an undesirable display method because, when the teletext display is scrolled, also the channel selection display must be scrolled similarly. As described above, when a desired display is to be conducted, the preset values of the registers must be previously considered. Moreover, the prior art system has a drawback that the process of the multiline display is so complicated that the load on the software is increased.